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TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 1 post office box 1443 ? houston, texas 772511443 cmos/ eeprom/ eprom technologies on a single device mask-rom devices for high-volume production one-time-programmable (otp) eprom devices for low-volume production reprogrammable-eprom devices for prototyping purposes internal system memory configurations on-chip program memory versions rom: 8k bytes eprom: 8k bytes data eeprom: 256 bytes static ram: 256 bytes usable as registers flexible operating features low-power modes: standby and halt commercial, industrial, and automotive temperature ranges clock options divide-by-1 (2 mhz 5 mhz sysclk) phase-locked loop (pll) divide-by-4 (0.5 mhz 5 mhz sysclk) supply voltage (v cc ) 5 v 10% programmable acquisition and control timer (pact) module input capture on up to six pins, four of which can have a programmable prescaler one input capture pin can drive an 8-bit event counter up to eight timer-driven outputs interaction between event counter and timer activity 18 independent interrupt vectors watchdog with selectable time-out period asynchronous mini serial communication interface (mini sci) flexible interrupt handling two software-programmable interrupt levels global- and individual-interrupt masking programmable rising- or falling-edge detect individual-interrupt vectors eight-channel 8-bit analog-to-digital converter 1 (adc1) TMS370 series compatibility register-to-register architecture 256 general-purpose registers 14 powerful addressing modes instructions upwardly compatible with all TMS370 devices cmos/ ttl compatible i / o pins / packages all peripheral function pins software configurable for digital i / o 14 bidirectional pins, nine input pins 44-pin plastic and ceramic leaded chip carrier (lcc) packages workstation / pc-based development system c compiler and c source debugger real-time in-circuit emulation multi-window user interface microcontroller programmer extensive breakpoint/trace capability production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. copyright ? 1997, texas instruments incorporated please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. op2 mc xtal2/clkin xtal1 cp2 scirxd cp6 an7 an6 an5 an4 v ss3 39 38 37 36 35 34 33 32 31 30 29 18 19 7 8 9 10 11 12 13 14 15 16 17 int1 int2 int3 v cc1 v cc3 a7 a6 v ss1 a5 a4 a3 20 21 22 23 fz and fn packages (top view) op5 op1 scitxd cp1 54321 644 reset op8 op7 op6 op4 op3 an0 an1 an2 an3 a1 a0 d7/cp5 d4/cp3 d3 d6/cp4 42 41 40 43 24 25 26 27 28 a2
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 2 post office box 1443 ? houston, texas 772511443 pin descriptions 44 pins i/o 2 description name no. i/o 2 description a0 a1 a2 a3 a4 a5 a6 a7 20 19 18 17 16 15 13 12 i/o port a is a general-purpose bidirectional i / o port. d3 d4/cp3 d6/cp4 d7/cp5 23 22 24 21 i/o port d is a general-purpose bidirectional port. also configurable as sysclk (see note 1) pact input capture 3 (see note 2) pact input capture 4 (see note 2) pact input capture 5 (see note 2) cp1 cp2 cp6 40 36 34 i pact input capture pin 1 pact input capture pin 2 pact input capture pin 3 an0/e0 an1/e1 an2/e2 an3/e3 an4/e4 an5/e5 an6/e6 an7/e7 25 26 27 28 30 31 32 33 i adc1 analog input pins (an0 an7) / port e digital input pins (e0 e7) port e can be programmed individually as a general-purpose digital input pin if it is not used as adc1 analog input or positive reference input. int1 int2 int3 7 8 9 i i/o i/o external interrupt (non-maskable or maskable) / general-purpose input pin external maskable interrupt input/general purpose bidirectional pin external maskable interrupt input/general purpose bidirectional pin op1 op2 op3 op4 op5 op6 op7 op8 42 43 44 1 2 3 4 5 o pact output pin 1 pact output pin 2 pact output pin 3 pact output pin 4 pact output pin 5 pact output pin 6 pact output pin 7 pact output pin 8 scirxd scitxd 35 41 i o pact mini sci data receive input pin pact mini sci data transmit output pin reset 6 i/o system reset bidirectional pin; as input pin, reset initializes the microcontroller; as open-drain output, reset indicates that an internal failure was detected by watchdog or oscillator fault circuit. mc 39 i mode control input pin; enables eeprom write protection override (wpo) mode, also eprom v pp xtal2 / clkin xtal1 38 37 i o internal oscillator crystal input / external clock source input internal oscillator output for crystal v cc1 v ss1 v cc3 v ss3 10 14 11 29 positive supply voltage for digital logic and digital i/o pins ground reference for digital logic and digital i/o pins adc1 positive supply voltage and optional positive reference input adc1 ground supply and low reference input pin 2 i = input, o = output notes: 1. d3 can be configured as sysclk by appropriately programming the dport1 and dport2 registers. 2. these digital i/o buffers are connected internally to some of the pact module's input capture pins. this allows the microcont roller to read the level on the input capture pin, or if the port d pin is configured as an output, to generate a capture. be careful to leave the port d pin configured as an input if the corresponding input capture pin is being driven by external circuitry.
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 3 post office box 1443 ? houston, texas 772511443 functional block diagram interrupts cp1 scitxd scirxd v system control clock options: divide-by-4 or divide-by-1 (pll) port a port d pact watchdog int1 e0-e7 or an0-an7 xtal1 xtal2/ clkin mc reset ss1 v cc1 program memory rom: 8k bytes eprom: 8k bytes ????? ????? data eeprom 256 bytes 4 8 a-to-d converter 1 v cc3 v ss3 mini sci cpu ram register file 256 bytes cp6 op1 op8 . . . . int2 int3 description the TMS370c032a, TMS370c332a, TMS370c732a, and se370c732a devices are members of the TMS370 family of single-chip 8-bit microcontrollers. unless otherwise noted, the term TMS370cx32 refers to these devices. the TMS370 family provides cost-effective real-time system control through integration of advanced peripheral-function modules and various on-chip memory configurations. the TMS370cx32 family of devices is implemented using high-performance silicon-gate cmos eprom and eeprom technologies. low-operating power, wide-operating temperature range, and noise immunity of cmos technology coupled with the high performance and extensive on-chip peripheral functions make the TMS370cx32 devices attractive for system designs for automotive electronics, industrial motors, computer peripheral controls, telecommunications, and consumer applications. all TMS370cx32 devices contain the following on-chip peripheral modules: programmable acquisition and control timer (pact) asynchronous mini sci pact watchdog timer eight channel, 8-bit analog-to-digital converter 1 (adc1)
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 4 post office box 1443 ? houston, texas 772511443 description (continued) table 1 provides a memory configuration overview of the TMS370cx32 devices. table 1. memory configurations device program memory (bytes) data memory (bytes) 44 pin packages rom eprom ram eeprom TMS370c032a 8k e 256 256 fn plcc TMS370c332a 8k e 256 e fn plcc TMS370c732a e 8k 256 256 fn plcc se370c732a 2 e 8k 256 256 fz clcc 2 system evaluators and development are for use only in prototype environment, and their reliability has not been characterized. the suffix letter (a) appended to the device names shown in the device column of table 1 indicates the configuration of the device. rom or eprom devices have different configurations as indicated in table 2. rom devices with the suffix letter a are configured through a programmable contact during manufacture. table 2. suffix letter configuration device 3 clock low-power mode eprom a divide-by-4 (standard oscillator) enabled rom a divide by 4 or divide by 1 (pll) enabled or disabled rom a di v ide - b y- 4 or di v ide - b y- 1 (pll) enabled or disabled 3 refer to the adevice numbering conventionso section for device nomenclature and to the adevice part numberso section for orderi ng. the 8k bytes of mask-programmable rom in the associated TMS370cx32 devices are replaced in the TMS370c732a with 8k bytes of eprom. all other available memory and on-chip peripherals are identical except for the TMS370c332a which does not have eeprom memory. the otp (TMS370c732a) and reprogrammable (se370c732a) devices are available. the TMS370c732a otp device is available in a plastic package. this microcontroller is effective to use for immediate production updates for other members of the TMS370cx32 family or for low-volume production runs when the mask charge or cycle time for the low-cost mask rom devices is not practical. the se370c732a has a windowed ceramic package to allow reprogramming of the program eprom memory during the development / prototyping phase of design. the se370c732a device allows quick updates to breadboards and prototype systems while iterating initial designs. the TMS370cx32 family provides two low-power modes (standby and halt) for applications where low-power consumption is critical. both modes stop all cpu activity (that is, no instructions are executed). in the standby mode, the internal oscillator, the pact counter, and pact's first command / definition entry remain active. this allows the pact module to bring the device out of standby mode. in the halt mode, all device activity is stopped. the device retains all ram data and peripheral configuration bits throughout both low-power modes. the TMS370cx32 features advanced register-to-register architecture that allows direct arithmetic and logical operations without requiring an accumulator (for example, add r24, r47; add the contents of register 24 to the contents of register 47 and store the result in register 47). the TMS370cx32 family is fully instruction-set-compatible, providing easy transition between members of the TMS370 8-bit microcontroller family. the TMS370cx32 has a pact module that acts as a timer coprocessor by gathering timing information on input signals and controlling output signals with little or no intervention by the cpu. the coprocessor nature of this module allows for levels of flexibility and power not found in traditional microcontroller timers.
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 5 post office box 1443 ? houston, texas 772511443 description (continued) the TMS370cx32 family provides the system designer with an economical, efficient solution to real-time control applications. the pact compact development tool (cdt ? ) solves the challenge of efficiently developing the software and hardware required to design the TMS370cx32 into an ever-increasing number of complex applications. the application source code can be written in assembly and c language, and the output code can be generated by the linker. precise real-time, in-circuit emulation and extensive symbolic debug and analysis tools ensure efficient software and hardware implementation as well as a reduced time-to-market cycle. the TMS370cx32 family together with the TMS370 pact cdt370, bp programmer, starter kit, software tools, the se370c732a reprogrammable devices, comprehensive product documentation, and customer support provide a complete solution to the needs of the system designer. central processing unit (cpu) the cpu on the TMS370cx32 device is the high-performance 8-bit TMS370 cpu module. the 'x32 implements an efficient register-to-register architecture that eliminates the conventional accumulator bottleneck. the complete 'x32 instruction map is shown in table 15. the '370cx32 cpu architecture provides the following components: cpu registers: a stack pointer (sp) that points to the last entry in the memory stack a status register (st) that monitors the operation of the instructions and contains the global interrupt-enable bits a program counter (pc) that points to the memory location of the next instruction to be executed a memory map that includes: 256-byte general-purpose ram that can be used for data memory storage, program instructions, general purpose register, dual-port ram, or the stack the upper 128-bytes of the register file is called dual-port ram that contains the capture registers, the circular buffer, and a command/definition area. a peripheral file that provides access to all internal peripheral modules, system-wide control functions, and eeprom/ eprom programming control 256-byte eeprom module that provides in-circuit programmability and data retention in power-off conditions 8k-byte rom or 8k-byte eprom cdt is a trademark of texas instruments incorporated.
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 6 post office box 1443 ? houston, texas 772511443 central processing unit (cpu) (continued) figure 1 illustrates the cpu registers and memory blocks. reserved 2 peripheral file 01ffh 0200h 1000h 10bfh 10c0h 1effh 1f00h 5fffh 6000h interrupts and reset vectors; trap vectors 0fffh reserved 2 7fffh 0 ram (includes up to 256-byte registers file) 0 15 program counter 7 legend: z=zero ie1 = level 1 interrupts enable c=carry v=overflow n=negative ie2 = level 2 interrupts enable ie1 ie2 z n c 0 1 2 3 4 5 6 7 v status register (st) stack pointer (sp) r0(a) r1(b) r3 r127 0000h 0001h 0002h 007fh r255 0003h r2 00ffh 1fffh 2000h 7f9ch 7f9bh 256-byte ram 00ffh 0100h 017fh 0180h 128-byte pact dual-port ram 0000h reserved 2 256-byte data eeprom reserved 2 8k-byte rom/eprom reserved 2 ffffh 8000h 2 reserved means the address space is reserved for future expansion. figure 1. programmer's model stack pointer (sp) the sp is an 8-bit cpu register. stack operates as a last-in, first-out, read / write memory. typically, the stack is used to store the return address on subroutine calls as well as the st contents during interrupt sequences. the sp points to the last entry or top of the stack. the sp is incremented automatically before data is pushed onto the stack and decremented after data is popped from the stack. the stack can be placed anywhere in the on-chip ram. status register (st) the st monitors the operation of the instructions and contains the global interrupt-enable bits. the st includes four status bits (condition flags) and two interrupt-enable bits. the four status bits indicate the outcome of the previous instruction; conditional instructions (for example, the conditional-jump instructions) use the status bits to determine program flow. the two interrupt-enable bits control the two interrupt levels.
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 7 post office box 1443 ? houston, texas 772511443 central processing unit (cpu) (continued) the st, status-bit notation, and status-bit definitions are shown in table 3. table 3. status registers 7 6 5 4 3 2 1 0 c n z v ie2 ie1 reserved reserved rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 r = read, w = write, 0 = value after reset program counter (pc) the contents of the pc point to the memory location of the next instruction to be executed. the pc consists of two 8-bit registers in the cpu: the program counter high (pch) and program counter low (pcl). these registers contain the most significant byte (msbyte) and least significant byte (lsbyte) of a 16-bit address. during reset, the contents of the reset vector (7ffeh, 7fffh) are loaded into the pc. the pch (msbyte of the pc) is loaded with the contents of memory location 7ffeh, and the pcl (lsbyte of the pc) is loaded with the contents of memory location 7fffh. figure 2 shows this operation using an example value of 6000h as the contents of the reset vector. memory program counter (pc) 60 00 pch pcl 60 00 0000h 7ffeh 7fffh figure 2. program counter after reset memory map the TMS370cx32 architecture is based on the von neuman architecture, where the program memory and data memory share a common address space. all peripheral input / output is memory mapped in this same common address space. as shown in figure 3, the TMS370cx32 provides memory-mapped ram, rom, eprom, data eeprom, i / o pins, peripheral functions, and system-interrupt vectors. the peripheral file contains all i / o port control, peripheral status and control, eeprom, eprom, and system-wide control functions. the peripheral file is located between 1000h to 107fh and is divided logically into eight peripheral file frames of 16 bytes each. the eight pf frames consist of five control frames and three reserved frames.each on-chip peripheral is assigned to a separate frame through which peripheral control and data information is passed.
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 8 post office box 1443 ? houston, texas 772511443 central processing unit (cpu) (continued) 256-byte ram (0000h00ffh) peripheral file reserved 2 7fc0h 7fdfh pact interrupt 1-18 7feeh 7ff7h reserved 2 7fech 7fedh interrupt 1 reset 1020h 102fh digital port control vectors adc1 7ffch 7ffdh 7ffeh 7fffh 0000h 0100h 0080h 0fffh 1000h 10bfh 10c0h 1effh 1f00h 1fffh 2000h 5fffh 6000h ffffh 00ffh interrupts and reset vectors; trap and pact vectors 7f9bh 7f9ch 7fffh 8000h 7ff8h 7ff9h 7ffah 7ffbh peripheral file control registers 1010h 101fh 1050h 105fh system control 1030h 103fh 1040h 104fh adc1 peripheral control trap 15 0 reserved 2 reserved 2 256-byte data eeprom reserved 2 8k-byte rom/eprom reserved 2 7f9ch 7fbfh 7fe0h 7febh 1000h 100fh 1060h 106fh 1070h 107fh reserved 2 pact peripheral control reserved 2 reserved 2 reserved 2 interrupt 2 interrupt 3 dualport ram (0080h00ffh) 2 reserved means that the address space is reserved for future expansion. figure 3. TMS370cx32 memory map ram/ register file (rf) locations within the ram address space can serve as the rf, general-purpose read / write memory, program memory, or the stack instructions. the TMS370cx32 devices contain 256 bytes of internal ram, memory-mapped beginning at location 0000h (r0) and continuing through location 00ffh (r255) which is shown in figure 1. the first two registers, r0 and r1, are also called register a and b, respectively. some instructions implicitly use register a or b; for example, the instruction ldsp (load sp) assumes that the value to be loaded into the stack pointer is contained in register b. registers a and b are the only registers cleared on reset. dual-port ram the upper 128 bytes of the register files (0080h 00ffh) can be used by the pact module to contain commands and definitions as well as timer values. any ram not used by pact can be used as additional cpu register or as general-purpose memory.
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 9 post office box 1443 ? houston, texas 772511443 peripheral file (pf) the TMS370cx32 control registers contain all the registers necessary to operate the system and peripheral modules on the device. the instruction set includes some instructions that access the pf directly. these instructions designate the register by the number of the pf relative to 1000h, preceded by p0 for a hexadecimal designator or p for a decimal designator. for example, the system-control register 0 (sccr0) is located at address 1010h; its peripheral file hexadecimal designator is p010, and its decimal designator is p16. table 4 shows the TMS370cx32 pf address map. table 4. TMS370cx32 peripheral file address map address range peripheral file designator description 1000h 100fh p000 p00f reserved 1010h 101fh p010 p01f system and eprom / eeprom control registers 1020h 102fh p020 p02f digital i / o port control registers 1030h 103fh p030 p03f reserved 1040h 104fh p040 p04f pact registers 1050h 106fh p050 p06f reserved 1070h 107fh p070 p07f analog-to-digital converter 1 registers 1080h 10ffh p080 p0ff reserved data eeprom the TMS370cx32 devices, containing 256 bytes of data eeprom, have a memory that is mapped beginning at location 1f00h and continuing through location 1fffh. writing to the data eeprom module is controlled by the data eeprom control register (deectl) and the write-protection register (wpr). programming algorithm examples are available in the TMS370 family user's guide (literature number spnu127) or the TMS370 family data manual (literature number spns014b). the data eeprom features include the following: programming: bit-, byte-, and block-write / erase modes internal charge pump circuitry. no external eeprom programming voltage supply is needed. control register: data eeprom programming is controlled by the deectl located in the pf frame beginning at location p01a. see table 5. in-circuit programming capability. there is no need to remove the device to program it. write protection. writes to the data eeprom are disabled during the following conditions. reset. all programming of the data eeprom module is halted. write protection active. there is one write-protect bit per 32-byte eeprom block. low-power mode operation write protection can be overridden by applying 12 v to mc. table 5. data eeprom and program eprom control registers memory map address symbol name p01a deectl data eeprom control register p01b e reserved p01c epctll program eprom control register low array
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 10 post office box 1443 ? houston, texas 772511443 program eprom 2 the TMS370c732 device contains 8k bytes of eprom mapped, beginning at location 6000h and continuing through location 7fffh as shown in figure 3. reading the program eprom modules is identical to reading other internal memory. during programming, the eprom is controlled by the eprom control register (epctll). the program eprom module features include: programming in-circuit programming capability if v pp is applied to mc control register: eprom programming is controlled by the eprom control register (epctll) located in the peripheral file (pf) frame at location p01c as shown in table 5. write protection: writes to the program eprom are disabled under the following conditions: reset: all programming to the eprom module is halted low-power modes 13 v not applied to mc program rom 2 the program rom consists of 8k bytes of mask programmable read-only memory. the program rom is used for permanent storage of data or instructions. programming of the mask rom is performed at the time of device fabrication. refer to figure 3 for rom memory map. system reset the system-reset operation ensures an orderly start-up sequence for the TMS370cx32 cpu-based device. there are up to three different actions that can cause a system reset to the device. two of these actions are generated internally, while one (reset pin) is controlled externally. these actions are as follows: pact watchdog (wd) timer. a watchdog-generated reset occurs if an improper value is written to the wd key register, or if the re-initialization does not occur before the watchdog timer timeout . see the TMS370 family user's guide (literature number spnu127) for more information. oscillator reset. reset occurs when the oscillator operates outside of the recommended operating range. see the TMS370 family user's guide (literature number spnu127) for more information. external reset pin. a low level signal can trigger an external reset. to ensure a reset, the external signal should be held low for one sysclk cycle. signals of less than one sysclk can generate a reset. see the TMS370 family user's guide (literature number spnu127) for more information. once a reset source is activated, the external reset pin is driven (active) low for a minimum of eight sysclk cycles. this allows the 'x32 device to reset external system components. additionally, if a cold start condition (v cc is off for several hundred milliseconds) or oscillator failure occurs or the reset pin is held low, then the reset logic holds the device in a reset state for as long as these actions are active. after a reset, the program can check the oscillator-fault flag (osc flt flag, sccr0.4) and the cold-start flag (cold start, sccr0.7) to determine the source of the reset. a reset does not clear these flags. table 6 depicts the reset sources. if none of the sources indicated in table 1 caused the reset, then the reset pin was pulled low by the external hardware or the pact module's watchdog. 2 memory addresses 7fe0h through 7febh are reserved for texas instruments, and 7fech through 7fffh are reserved for interrupt and reset vectors. trap vectors, used with trap0 through trap15 instructions are located between addresses 7fc0h and 7fdfh. pact interrup ts are located between addresses 7f9ch and 7fbfh.
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 11 post office box 1443 ? houston, texas 772511443 system reset (continued) table 6. reset sources register address pf bit no. control bit source of reset sccr0 1010h p010 7 cold start cold (power-up) sccr0 1010h p010 4 osc flt flag oscillator out of range once a reset is activated, the following sequence of events occurs: 1. the cpu registers are initialized: st = 00h, sp = 01h (reset state). 2. registers a and b are initialized to 00h (no other ram is changed). 3. the contents of the lsbyte of the reset vector (07ffh) are read and stored in the pcl. 4. the contents of the msbyte of the reset vector (07feh) are read and stored in the pch. 5. program execution begins with an opcode fetch from the address pointed to the pc. the reset sequence takes 20 sysclk cycles from the time the reset pulse is released until the first opcode fetch. during a reset, ram contents (except for registers a and b) remain unchanged, and the module control register bits are initialized to their reset state.
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 12 post office box 1443 ? houston, texas 772511443 interrupts the TMS370 family software-programmable interrupt structure permits flexible on-chip and external interrupt configurations to meet real-time interrupt-driven application requirements. the hardware interrupt structure incorporates two priority levels as shown in figure 4. interrupt level 1 has a higher priority than interrupt level 2. the two priority levels can be masked independently by the global interrupt mask bits (ie1 and ie2) of the st. group 2 cpu nmi logic enable ie1 ie2 level 1 int level 2 int pact 3 pri priority cmd/def entry 7 cmd/def entry 6 cmd/def entry 5 cmd/def entry 4 cmd/def entry 3 cmd/def entry 2 ad int ad pri adc1 status reg ext int1 int1 pri int1 cmd/def entry 1 cmd/def entry 0 group 3 pact 1 pri overflow cp1 edge cp2 edge cp3 edge cp4 edge cp5 edge cp6 edge circular buffer group 1 pact 2 pri sci txint sci rxint pact default timer ext int3 int3 ext int2 int2 int3 pri int2 pri figure 4. interrupt control each system interrupt is configured independently to either the high- or low-priority chain by the application program during system initialization. within each interrupt chain, the interrupt priority is fixed by the position of the system interrupt. however, since each system interrupt is selectively configured on either the high- or low-priority-interrupt chain, the application program can elevate any system interrupt to the highest priority. arbitration between the two priority levels is performed within the cpu. arbitration within each of the priority
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 13 post office box 1443 ? houston, texas 772511443 interrupts (continued) chains is performed within the peripheral modules to support interrupt expansion for future modules. pending interrupts are serviced upon completion of current instruction execution, depending on their interrupt mask and priority conditions. the TMS370cx32 has 22 hardware system interrupts (plus reset ) as shown in table 7. each system interrupt has a dedicated vector located in program memory through which control is passed to the interrupt service routines. a system interrupt may have multiple interrupt sources. all the interrupt sources are individually maskable by local interrupt enable control bits in the associated peripheral file. each interrupt source flag bit is individually readable for software polling or for determining which interrupt source generated the associated system interrupt. nineteen of the system interrupts are generated by on-chip peripheral functions, and three external interrupts are supported. software configuration of the external interrupts is performed through the int1, int2, and int3 control registers in peripheral file frame 1. each external interrupt is individually software configurable for input polarity (rising or falling edge) for ease of system interface. external interrupt int1 is software configurable as either a maskable or non-maskable interrupt. when int1 is configured as non-maskable, it cannot be masked by the individual- or global-enable mask bits. the int1 nmi bit is protected during non-privileged operation and, therefore, should be configured during the initialization sequence following reset. to maximize pin flexibility, external interrupts int2 and int3 can be software configured as general-purpose input/output pins if the interrupt function is not required (int1 can be similarly configured as an input pin).
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 14 post office box 1443 ? houston, texas 772511443 interrupts (continued) table 7. hardware system interrupts interrupt source interrupt flag osc flt flg system interrupt vector address module priority 2 priority in group reset external reset watchdog overflow oscillator fault cold start (no flag) osc flt flag reset 3 7ffeh, 7fffh 1 1 int1 external interrupt 1 int1 flag int1 3 7ffch, 7ffdh 2 1 int2 external interrupt 2 int2 flag int2 3 7ffah, 7ffbh 3 1 int3 external interrupt 3 int3 flag int3 3 7ff8h, 7ff9h 4 1 pact circular buffer buffer half/full interrupt flag bufint 7fb0h, 7fb1h 1 pact cp6 event cp6 int flag cp6int 7fb2h, 7fb3h 2 pact cp5 event cp5 int flag cp5int 7fb4h, 7fb5h 3 pact (grou p 1) pact cp4 event cp4 int flag cp4int 7fb6h, 7fb7h 5 4 pact (gro u p 1) pact cp3 event cp3 int flag cp3int 7fb8h, 7fb9h 5 5 pact cp2 event cp2 int flag cp2int 7fbah, 7fbbh 6 pact cp1 event cp1 int flag cp1int 7fbch, 7fbdh 7 default timer overflow deftim ovrfl int flag povrl int 7fbeh, 7fbfh 8 pact (grou p 2) pact sci rx int pact rx rdy prxint 7f9eh, 7f9fh 6 1 pact (gro u p 2) pact sci tx int pact tx rdy ptxint 7f9ch, 7f9dh 6 2 pact cmd/def entry 0 cmd/def int 0 flag cdint 0 7fa0h, 7fa1h 1 pact cmd/def entry 1 cmd/def int 1 flag cdint 1 7fa2h, 7fa3h 2 pact cmd/def entry 2 cmd/def int 2 flag cdint 2 7fa4h, 7fa5h 3 pact (grou p 3) pact cmd/def entry 3 cmd/def int 3 flag cdint 3 7fa6h, 7fa7h 7 4 pact (gro u p 3) pact cmd/def entry 4 cmd/def int 4 flag cdint 4 7fa8h, 7fa9h 7 5 pact cmd/def entry 5 cmd/def int 5 flag cdint 5 7faah, 7fabh 6 pact cmd/def entry 6 cmd/def int 6 flag cdint 6 7fach, 7fadh 7 pact cmd/def entry 7 cmd/def int 7 flag cdint 7 7faeh, 7fafh 8 adc1 adc1 conversion complete ad int flag adint 7fech, 7fedh 8 1 2 relative priority within an interrupt level 3 release microcontroller from standby and halt low-power modes privileged operation and eeprom write protection override the TMS370cx32 family is designed with significant flexibility to enable the designer to software-configure the system and peripherals to meet the requirements of a variety of applications. the nonprivileged mode of operation ensures the integrity of the system configuration, once it is defined for an application. following a hardware reset, the TMS370cx32 operates in the privileged mode, where all peripheral file registers have unrestricted read / write access, and the application program configures the system during the initialization sequence following reset. as the last step of system initialization, the privilege disable bit (sccr2.0) is set to 1 to enter the nonprivileged mode, disabling write operations to specific configuration-control bits within the pf. table 8 displays the system-configuration bits which are write-protected during the nonprivileged mode and must be configured by software prior to exiting the privileged mode.
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 15 post office box 1443 ? houston, texas 772511443 privileged operation and eeprom write protection override (continued) table 8. privilege bits register 2 control bit name location control bit sccro p010.5 p010.6 pf auto wait osc power sccr1 p011.2 p011.4 memory disable autowait disable sccr2 p012.0 p012.1 p012.3 p012.4 p012.6 p012.7 privilege disable int1 nmi cpu stest bus stest pwrdwn / idle halt / standby pactscr p040.0 p040.1 p040.2 p040.3 p040.4 pact prescale select 0 pact prescale select 1 pact prescale select 2 pact prescale select 3 fast mode select pactpri p04f.0 p04f.1 p04f.2 p04f.3 p04f.4 p04f.5 p04f.7 pact wd prescale select 0 pact wd prescale select 1 pact mode select pact group 3 priority pact group 2 priority pact group 1 priority pact stest adpri p07f.5 p07f.6 p07f.7 ad espen ad priority ad stest 2 the privilege bits are shown in a bold typeface in the peripheral file frame 1 section. low-power and idle modes the TMS370cx32 devices have two low-power modes (standby and halt) and an idle mode. for mask-rom devices, low-power modes can be disabled permanently through a programmable contact at the time when the mask is manufactured. the standby and halt low-power modes significantly reduce power consumption by reducing or stopping the activity of the various on-chip peripherals when processing is not required. each of the low-power modes is entered by executing the idle instruction when the pwrdwn / idle bit in sccr2 has been set to 1. the halt / standby bit in sccr2 controls the low-power mode selection. in the standby mode (halt / standby = 0), all cpu activity and most peripheral module activity is stopped; however, the oscillator, internal clocks, the pact counter, and the first pact command entry remain active in all modules. system processing is suspended until a qualified interrupt (hardware reset or external interrupt on int1, int2, or int3) is detected. in the halt mode (halt / standby = 1), the TMS370cx32 is placed in its lowest power consumption mode. the oscillator and internal clocks are stopped, causing all internal activity to be halted. system activity is suspended until a qualified interrupt (hardware reset or external interrupt on the int1, int2, or int3) is detected. the power-down mode-selection bits are summarized in table 9.
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 16 post office box 1443 ? houston, texas 772511443 low-power and idle modes (continued) table 9. low-power / idle control bits power-down control bits pwrdwn / idle (sccr2.6) halt / standby (sccr2.7) mode selected 1 0 standby 1 1 halt 0 x 2 idle 2 x = don't care when low-power modes are disabled through a programmable contact in the mask-rom devices, writing to the sccr2.6-7 bits is ignored. in addition, if an idle instruction is executed when low-power modes are disabled through a programmable contact, the device always enters the idle mode. to provide a method for always exiting low-power modes for mask-rom devices, int1 is enabled automatically as a nonmaskable interrupt (nmi) during low-power modes when the hard watchdog mode is selected. this means that the nmi is generated always, regardless of the interrupt enable flags. the following information is preserved throughout both the standby and halt modes: ram (register file), cpu registers (sp, pc, and st), i / o pin direction and output data, and status registers of all on-chip peripheral functions. since all cpu instruction processing is stopped during the standby and halt modes, the clocking of the wd timer is inhibited. clock modules the 'x32 family provides two clock options that are referred to as divide-by-1 (phase-locked loop) and divide-by-4 (standard oscillator). both the divide-by-1 and divide-by-4 options are configurable during the manufacturing process of a TMS370 microcontroller. the 'x32 masked-rom devices offer both options to meet system engineering requirements. only one of the two clock options is allowed on each rom device. the '732a eprom has only the divide-by-4. the divide-by-1 clock module option provides the capability for reduced electromagnetic interference (emi) with no added cost. the divide-by-1 provides a one-to-one match of the external resonator frequency (clkin) to the internal system clock (sysclk) frequency, whereas the divide-by-4 produces a sysclk which is one-fourth the frequency of the external resonator. inside the divide-by-1 module, the frequency of the external resonator is multiplied by four, and the clock module then divides the resulting signal by four to provide the four-phased internal system clock signals. the resulting sysclk is equal to the resonator frequency. these are formulated as follows: divide-by-4 option : sysclk external resonator frequency 4 clkin 4 divide-by-1 option : sysclk external resonator frequency 4 4 clkin the main advantage of choosing a divide-by-1 oscillator is the reduced emi. the harmonics of low-speed resonators extend through fewer of the emissions spectrum than the harmonics of faster resonators. the divide-by-1 provides the capability of reducing the resonator speed by four times, and this results in a steeper decay of emissions produced by the oscillator.
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 17 post office box 1443 ? houston, texas 772511443 system configuration registers table 10, contains system-configuration and control functions and registers for controlling eeprom programming. the privileged bits are shown in a bold typeface and shaded areas. table 10. peripheral file frame 1: system-configuration registers pf bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reg p010 cold start osc power pf auto wait osc flt flag mc pin wpo mc pin data e m p/ m c mode sccr0 p011 e e e auto wait disable e memory disable e e sccr1 p012 halt / standby pwrdwn / idle e bus stest cpu stest e int1 nmi privilege disable sccr2 p013 to p016 reserved p017 int1 flag int1 pin data e e e int1 polarity int1 priority int1 enable int1 p018 int2 flag int2 pin data e int2 data dir int2 data out int2 polarity int2 priority int2 enable int2 p019 int3 flag int3 pin data e int3 data dir int3 data out int3 polarity int3 priority int3 enable int3 p01a busy e e e e ap w1w0 exe deectl p01b reserved p01c busy vpps e e e e w0 exe epctll p01d p01e p01f reserved
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 18 post office box 1443 ? houston, texas 772511443 digital port control registers peripheral file frame 2 contains the digital i/o pin configuration and control registers. table 11 shows the specific addresses, registers, and control bits within this peripheral file frame. table 12 shows the port configuration register setup. table 11. peripheral file frame 2: digital port-control registers pf bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p020 reserved aport1 p021 port a control register 2 (must be 0) aport2 p022 port a data adata p023 port a direction adir p024 to p02b reserved p02c port d control register 1 (must be 0) e port d control register 1 (must be 0) e e e dport1 p02d port d control register 2 (must be 0) 2 e port d control register 2 (must be 0) 2 e e e dport2 p02e port d data e port d data e e e ddata p02f port d direction e port d direction e e e ddir 2 to configure pin d3 as sysclk, set port d control register 2 = 08h. table 12. port configuration register setup port pin abcd 00q1 abcd 00y0 a 0 7 data out q data in y d 3, 4, 6, 7 data out q data in y a = port x control register 1 b = port x control register 2 c = data d = direction programmable acquisition and control timer (pact) module traditionally, timers in microcontrollers provide limited capture and compare functions consuming significant cpu processing power, leading to inaccurate timings due to interrupt latencies. the programmable acquisition and control timer (pact8) acts as a coprocessor combining configurable capture and compare features, within a flexible dual-port ram, able to run real-time tasks with little or no cpu intervention. the pact structure allows concatenation of tasks, thus enabling the cpu to perform data manipulation while the pact module both captures and outputs real-time-related information. since all the pact control information is held within the dual-port ram, the cpu can access these parameters quickly. to use the pact, the user must set up three distinct areas of memory. the first is the dual-port ram, which contains the capture area, the commands, and the timer definitions. the second is the peripheral frame. the third is an area near the end of the program memory which holds the interrupt vectors of pact.
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 19 post office box 1443 ? houston, texas 772511443 programmable acquisition and control timer (pact) module (continued) the pact module features include the following: input-capture functions on up to six input pins (cp1 to cp6), depending on the mode selected: mode a: cp12 are dedicated capture, cp36 are circular-buffer capture, and cp6 is an event pin. mode b: cp14 are dedicated capture, cp56 are circular-buffer capture, and cp6 is an event pin. multiple timer-driven outputs on eight pins (op1 to op8) standard compare command: sets or clears an output pin whenever the timer/counter is equal to a certain value virtual timers: enable variations of the pwm's period and provides periodic interrupts to the processor. double event-compare command: comparisons of the 8-bit event counter with two event-compare values and the actions that can be performed are based on each value. event-compare 1 matching the event counter: sets or resets the selected output pin (op1op8), generates interrupt, and generates a 32-bit capture into the circular buffer. event-compare 2 matching the event counter: sets or resets the selected output pin (op1op8), generates interrupt, generates a 32-bit capture into the circular buffer, and resets the 20-bit default timer. offset timer definition-time from last event: generates an interrupt when the maximum event count is reached stores the 16-bit virtual timer in the circular buffer on each event stores the 20-bit default timer and 8-bit event counter in the circular buffer when the maximum event count is reached resets the 20-bit hardware default timer when the maximum event count is reached conditional-compare command has a timer-compare value and an event-compare value. generates an interrupt when the event-compare value equals the event counter and the timer-compare value equals the last defined timer sets or clears one of the seven output pins (op1op7) when the event compare value equals the event counter and the timer-compare value equals the last defined timer baud rate timer definition: runs the mini-serial communications port built into the pact module. configurable timer overflow rates one 8-bit event counter driven by cp6 up to 20-bit timer capability interaction between event counter and timer activity register-based organization allowing direct access to timer parameters by the cpu 18 independent interrupt vectors with two priority levels integrated, configurable watchdog with selectable time-out period
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 20 post office box 1443 ? houston, texas 772511443 programmable acquisition and control timer (pact) module (continued) mini-serial communications interface works as a simplified full duplex universal asychronous receiver / transmitter (uart) with independent setup of baud rate for receive and transmit lines. asynchronous communications mode asynchronous baud 1 (max virtual timer value) (4) (pact resolution) 2 where pact resolution = sysclk prescale value pact block diagram the pact module block diagram is illustrated in figure 5. 8-bit event counter 20-bit timer / counter prescale reset watchdog timer dedicated capture register 1 dedicated capture register 2 dedicated capture register 3 dedicated capture register 4 circular buffer (32bit captures) command analyzer and output controller command / definition area mini sci pact prescaled clock 3-bit prescaler outputs int level 1 int level 2 opt1 opt3 opt2 opt4 opt5 opt6 opt7 opt8 scitxd scirxd mode event only cp1 cp2 cp3 cp4 cp5 cp6 figure 5. pact block diagram
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 21 post office box 1443 ? houston, texas 772511443 pact control registers the pact module is controlled and accessed through registers in peripheral frame 4. these registers are listed in table 13. the bits in shaded boxes are privileged mode bits; that is, they can be written to only in the privileged mode. table 13. pact control registers pf bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reg p040 deftim ovrfl int ena deftim ovrfl int flag cmd/def area ena fast mode select pact prescale select3 pact prescale select2 pact prescale select1 pact prescale select0 pactscr p041 cmd/def area int ena e cmd/def area start bit 5 cmd/def area start bit 4 cmd/def area start bit 3 cmd/def area start bit 2 e e cdstart p042 e cmd/def area end bit 6 cmd/def area end bit 5 cmd/def area end bit 4 cmd/def area end bit 3 cmd/def area end bit 2 e e cdend p043 1 1 buffer pointer bit 5 buffer pointer bit 4 buffer pointer bit 3 buffer pointer bit 2 buffer pointer bit 1 e bufptr p044 reserved p045 pact rxrdy pact txrdy pact parity pact fe pact sci rx int ena pact sci tx int ena e pact sci sw reset scictlp p046 pact rxdt7 pact rxdt6 pact rxdt5 pact rxdt4 pact rxdt3 pact rxdt2 pact rxdt1 pact rxdt0 rxbufp p047 pact txdt7 pact txdt6 pact txdt5 pact txdt4 pact txdt3 pact txdt2 pact txdt1 pact txdt0 txbufp p048 pact op8 state pact op7 state pact op6 state pact op5 state pact op4 state pact op3 state pact op2 state pact op1 state pstate p049 cmd/def int 7 flag cmd/def int 6 flag cmd/def int 5 flag cmd/def int 4 flag cmd/def int 3 flag cmd/def int 2 flag cmd/def int 1 flag cmd/def int 0 flag cdflags p04a cp2 int ena cp2 int flag cp2 capt rising edge cp2 capt falling edge cp1 int ena cp1 int flag cp1 capt rising edge cp1 capt falling edge cpctl1 p04b cp4 int ena cp4 int flag cp4 capt rising edge cp4 capt falling edge cp3 int ena cp3 int flag cp3 capt rising edge cp3 capt falling edge cpctl2 p04c cp6 int ena cp6 int flag cp6 capt rising edge cp6 capt falling edge cp5 int ena cp5 int flag cp5 capt rising edge cp5 capt falling edge cpctl3 p04d buffer half/full int ena buffer half/full int flag input capt prescale select 3 input capt prescale select 2 input capt prescale select 1 cp6 event only event counter sw reset op/ set/clr select cppre p04e watchdog reset key wdrst p04f pact stest pact suspend pact group 1 priority pact group 2 priority pact group 3 priority pact mode select pact wd prescale select 1 pact wd prescale select 0 pactpri
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 22 post office box 1443 ? houston, texas 772511443 analog-to-digital converter 1 module the analog-to-digital converter 1 (adc1) module is an 8-bit, successive approximation converter with internal sample-and-hold circuitry. the module has four multiplexed analog input channels that allow the processor to convert the voltage levels from up to eight different sources. the adc1 module features include the following: minimum conversion time: 32.8 m s at 5 mhz sysclk ten external pins: eight analog-input channels (an0 an7), any of which can be software-configured as digital inputs (e0 e7) when not needed as analog channels an1 an7 also can be configured as positive-input voltage reference. v cc3 : adc1 module high-voltage reference input v ss3 : adc1 module low-voltage reference input the addata register, which contains the digital result of the last adc1 conversion. adc1 operations can be accomplished through either interrupt-driven or polled algorithms. six adc1 module control registers located in the control-register frame beginning at address 1070h the adc1 module control registers are listed in table 14. table 14. adc1 module control register memory map pf bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reg p070 convert start sample start ref volt select2 ref volt select1 ref volt select0 ad input select2 ad input select1 ad input select0 adctl p071 e e e e e ad ready ad int flag ad int ena adstat p072 a/d conversion data register addata p073 to p07c reserved p07d port e data input register adin p07e port e input enable register adena p07f ad stest ad priority ad espen e e e e e adpri
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 23 post office box 1443 ? houston, texas 772511443 analog-to-digital converter 1 module (continued) the adc1 module block diagram is illustrated in figure 6. adctl.5 3 5 4 3 adena.0 ref volts select adctl.2 0 2 1 0 ad input select adin.0 port e input ena 0 port e data an 0 an0 adena.1 adin.1 port e input ena 1 port e data an 1 an1 adena.2 adin.2 port e input ena 2 port e data an 2 an2 adena.3 adin.3 port e input ena 3 port e data an 3 an3 adena.4 adin.4 port e input ena 4 port e data an 4 an4 adena.5 adin.5 port e input ena 5 port e data an 5 an5 adena.6 adin.6 port e input ena 6 port e data an 6 an6 adena.7 adin.7 port e input ena 7 port e data an 7 an7 v cc3 v ss3 adctl.6 sample start adctl.7 convert start addata.7 0 a-to-d conversion data register adstat.2 ad ready ad priority adpri.6 0 1 level 1 int level 2 int ad int flag adstat.1 ad int ena adstat.0 a/d figure 6. adc1 block diagram
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 24 post office box 1443 ? houston, texas 772511443 instruction set overview table 15 provides an opcode to instruction cross reference of all 73 instructions and 274 opcodes of the `370cx32 instruction set. the numbers at the top of this table represent the most significant nibble (msn) of the opcode while the numbers at the left side of the table represent the least significant nibble (lsn). the instruction of these two opcode nibbles contains the mnemonic, operands, and byte / cycle particular to that opcode. for example, the opcode b5h points to the clr a instruction. this instruction contains one byte and executes in eight sysclk cycles.
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 post office box 1443 houston, texas 772511443 ? 25 table 15. TMS370 family opcode/instruction map 2 msn 01 2 3 4 5 6 7 8 9 a b c d e f 0 jmp #ra 2/7 incw #ra,rd 3/11 mov ps,a 2/8 clrc / tst a 1/9 mov a,b 1/9 mov a,rd 2/7 trap 15 1/14 ldst n 2/6 1 jn ra 2/5 mov a,pd 2/8 mov b,pd 2/8 mov rs,pd 3/10 mov ps,b 2/7 mov b,rd 2/7 trap 14 1/14 mov #ra[sp],a 2/7 2 jz ra 2/5 mov rs,a 2/7 mov #n,a 2/6 mov rs,b 2/7 mov rs,rd 3/9 mov #n,b 2/6 mov b,a 1/8 mov #n,rd 3/8 mov ps,rd 3/10 dec a 1/8 dec b 1/8 dec rd 2/6 trap 13 1/14 mov a,*ra[sp] 2/7 3 jc ra 2/5 and rs,a 2/7 and #n,a 2/6 and rs,b 2/7 and rs,rd 3/9 and #n,b 2/6 and b,a 1/8 and #n,rd 3/8 and a,pd 2/9 and b,pd 2/9 and #n,pd 3/10 inc a 1/8 inc b 1/8 inc rd 2/6 trap 12 1/14 cmp *n[sp],a 2/8 4 jp ra 2/5 or rs,a 2/7 or #n,a 2/6 or rs,b 2/7 or rs,rd 3/9 or #n,b 2/6 or b,a 1/8 or #n,rd 3/8 or a,pd 2/9 or b,pd 2/9 or #n,pd 3/10 inv a 1/8 inv b 1/8 inv rd 2/6 trap 11 1/14 extend inst,2 opcodes l s n 5 jpz ra 2/5 xor rs,a 2/7 xor #n,a 2/6 xor rs,b 2/7 xor rs,rd 3/9 xor #n,b 2/6 xor b,a 1/8 xor #n,rd 3/8 xor a,pd 2/9 xor b,pd 2/9 xor #n,pd 3/10 clr a 1/8 clr b 1/8 clr rn 2/6 trap 10 1/14 n 6 jnz ra 2/5 btjo rs,a,ra 3/9 btjo #n,a,ra 3/8 btjo rs,b,ra 3/9 btjo rs,rd,ra 4/11 btjo #n,b,ra 3/8 btjo b,a,ra 2/10 btjo #n,rd,ra 4/10 btjo a,pd,ra 3/11 btjo b,pd,ra 3/10 btjo #n,pd,ra 4/11 xchb a 1/10 xchb a / tst b 1/10 xchb rn 2/8 trap 9 1/14 idle 1/6 7 jnc ra 2/5 btjz rs.,a,ra 3/9 btjz #n,a,ra 3/8 btjz rs,b,ra 3/9 btjz rs,rd,ra 4/11 btjz #n,b,ra 3/8 btjz b,a,ra 2/10 btjz #n,rd,ra 4/10 btjz a,pd,ra 3/10 btjz b,pd,ra 3/10 btjz #n,pd,ra 4/11 swap a 1/11 swap b 1/11 swap rn 2/9 trap 8 1/14 mov #n,pd 3/10 8 jv ra 2/5 add rs,a 2/7 add #n,a 2/6 add rs,b 2/7 add rs,rd 3/9 add #n,b 2/6 add b,a 1/8 add #n,rd 3/8 movw #16,rd 4/13 movw rs,rd 3/12 movw #16[b],rpd 4/15 push a 1/9 push b 1/9 push rd 2/7 trap 7 1/14 setc 1/7 9 jl ra 2/5 adc rs,a 2/7 adc #n,a 2/6 adc rs,b 2/7 adc rs,rd 3/9 adc #n,b 2/6 adc b,a 1/8 adc #n,rd 3/8 jmpl lab 3/9 jmpl *rp 2/8 jmpl *lab[b] 3/11 pop a 1/9 pop b 1/9 pop rd 2/7 trap 6 1/14 rts 1/9 a jle ra 2/5 sub rs,a 2/7 sub #n,a 2/6 sub rs,b 2/7 sub rs,rd 3/9 sub #n,b 2/6 sub b,a 1/8 sub #n,rd 3/8 mov & lab,a 3/10 mov *rp,a 2/9 mov *lab[b],a 3/12 djnz a,#ra 2/10 djnz b,#ra 2/10 djnz rd,#ra 3/8 trap 5 1/14 rti 1/12 b jhs ra 2/5 sbb rs,a 2/7 sbb #n,a 2/6 sbb rs,b 2/7 sbb rs,rd 3/9 sbb #n,b 2/6 sbb b,a 1/8 sbb #n,rd 3/8 mov a, & lab 3/10 mov a, *rp 2/9 mov a,*lab[b] 3/12 compl a 1/8 compl b 1/8 compl rd 2/6 trap 4 1/14 push st 1/8 2 all conditional jumps (opcodes 01 0f), btjo, btjz, and djnz instructions use two additional cycles if the branch is taken. the btjo, btjz, and djnz instructions have a relative address as the last operand. l
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 t emp l ate r e l ease d ate: 7 11 94 26 post office box 1443 houston, texas 772511443 ? table 15. TMS370 family opcode/instruction map 2 (continued) msn 01 2 3 4 5 6 7 8 9 a b c d e f c jnv ra 2/5 mpy rs,a 2/46 mpy #n,a 2/45 mpy rs,b 2/46 mpy rs,rd 3/48 mpy #n,b 2/45 mpy b,a 1/47 mpy #n,rs 3/47 br lab 3/9 br *rp 2/8 br *lab[b] 3/11 rr a 1/8 rr b 1/8 rr rd 2/6 trap 3 1/14 pop st 1/8 l s d jge ra 2/5 cmp rs,a 2/7 cmp #n,a 2/6 cmp rs,b 2/7 cmp rs,rd 3/9 cmp #n,b 2/6 cmp b,a 1/8 cmp #n,rd 3/8 cmp & lab,a 3/11 cmp *rp,a 2/10 cmp *lab[b],a 3/13 rrc a 1/8 rrc b 1/8 rrc rd 2/6 trap 2 1/14 ldsp 1/7 s n e jg ra 2/5 dac rs,a 2/9 dac #n,a 2/8 dac rs,b 2/9 dac rs,rd 3/11 dac #n,b 2/8 dac b,a 1/10 dac #n,rd 3/10 call lab 3/13 call *rp 2/12 call *lab[b] 3/15 rl a 1/8 rl b 1/8 rl rd 2/6 trap 1 1/14 stsp 1/8 f jlo ra 2/5 dsb rs,a 2/9 dsb #n,a 2/8 dsb rs,b 2/9 dsb rs,rd 3/11 dsb #n,b 2/8 dsb b,a 1/10 dsb #n,rd 3/10 callr lab 3/15 callr *rp 2/14 callr *lab[b] 3/17 rlc a 1/8 rlc b 1/8 rlc rd 2/6 trap 0 1/14 nop 1/7 second byte of two-byte instructions (f4xx): f4 8 movw *n[rn] 4/15 div rn.a 3/14-63 f4 9 jmpl *n[rn] 4/16 legend: * = indirect addressing operand prefix & = direct addressing operand prefix f4 a mov *n[rn],a 4/17 # = immediate operand #16 = immediate 16-bit number lab = 16-label i di t 8 bit b f4 b mov a,*n[rn] 4/16 n = immediate 8-bit number pd = peripheral register containing destination type pn = peripheral register ps = peri p heral register containing source byte f4 c br *n[rn] 4/16 ps = peri heral register containing source byte ra = relative address rd = register containing destination type rn = re g ister file f4 d cmp *n[rn],a 4/18 rn register file rp = register pair rpd = destination register pair rps = source register pair f4 e call *n[rn] 4/20 rs = register containing source byte f4 f callr *n[rn] 4/22 2 all conditional jumps (opcodes 01 0f), btjo, btjz, and djnz instructions use two additional cycles if the branch is taken. the btjo, btjz, and djnz instructions have a relative address as the last operand.
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 27 post office box 1443 ? houston, texas 772511443 development system support the TMS370 family development support tools include an assembler, a c-compiler, a linker, a starter kit, cdt and an eeprom / uveprom programmer. assembler/ linker (part no. tmds374085002 for pc) includes extensive macro capability provides high-speed operation includes format conversion utilities for popular formats ansi c compiler (part no. tmds374085502 for pc, part no. tmds374055509 for hp700 ? , sun-3 ? or sun-4 ? ) generate assembly code for the TMS370 that can be inspected easily improves code execution speed and reduces code size with optional optimizer pass enables direct reference to the TMS370's port registers by using a naming convention provides flexibility in specifying the storage for data objects interfaces c functions and assembly functions easily includes assembler and linker cdt370 (compact development tool) pact real-time in-circuit emulation base (part number edscdt37p for pc, requires cable) cable for 44-pin plcc (part no. edstrg44plcc32) eeprom and eprom programming support allows inspection and modification of memory locations includes compatibility to upload / download program and data memory execute programs and software routines includes 1 024-sample trace buffer includes single-step executable instructions uses software breakpoints to halt program execution at selected address microcontroller programmer base (part no. tmds3760500a for pc, requires programmer head) single unit head for 44-pin plcc (part no. tmds3780510a) pc-based, window / function-key-oriented user interface for ease of use and rapid learning environment starter kit (part no. tmds37000 for pc) includes TMS370 assembler diskette and documentation includes TMS370 simulator includes programming adapter board and programming software does not include (to be supplied by the user): + 5 v power supply zif sockets 9-pin rs-232 cable hp700 is a trademark of hewlett-packard company. sun-3 and sun-4 are trademarks of sun microsystems, incorporated.
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 28 post office box 1443 ? houston, texas 772511443 device numbering conventions figure 7 illustrates the numbering and symbol nomenclature for the TMS370cx32 family. 7 370 32 c prefix: tms = standard prefix for fully qualified devices se = system evaluator (window eprom) that is used for prototyping purpose. family: 370 = TMS370 8-bit microcontroller family technology: c = cmos program memory types: 0 = mask rom 3 = mask rom, no data eeprom 7 = eprom device type: 32 = x32 device containing the following modules: analog-to-digital converter 1 programmable acquisition and control timer (pact) memory size: 2 = 8k bytes temperature ranges: a = 40 c to 85 c l = 0 c to 70 c t = 40 c to 105 c packages: fn = plastic leaded chip carrier fz = ceramic leaded chip carrier rom and eprom option: a = for rom device, the watchdog timer can be configured as one of the three different mask options: a standard watchdog or a hard watchdog or a simple watchdog the clock can be either: divide-by-4 clock or divide-by-1 (pll) clock the low-power modes can be either: enabled or disabled a = for eprom device, a standard watchdog, a divide-by- 4 clock, and low-power modes are enabled tms afnt figure 7. TMS370cx32 family nomenclature
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 29 post office box 1443 ? houston, texas 772511443 device part numbers table 16 lists all the 'x32 devices available. the device part number nomenclature is designed to assist ordering. upon ordering, the customer must specify not only the device part number, but also the clock and watchdog timer options desired. each device can have only one of the three possible watchdog timer options and one of the two clock options. the options to be specified pertain solely to orders involving rom devices. table 16. device part numbers device part numbers for 44 pins (lcc) TMS370c032afna TMS370c032afnl TMS370c032afnt TMS370c332afna TMS370c332afnl TMS370c332afnt TMS370c732afnt se370c732afzt 2 2 system evaluators are for use in prototype environment, and their reliability has not been characterized.
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 30 post office box 1443 ? houston, texas 772511443 new code release form figure 8 shows a sample of the new code release form. new code release form texas instruments TMS370 microcontroller products date: to release a new customer algorithm to ti incorporated into a TMS370 family microcontroller, complete this form and submit with the following information: 1. a rom description in object form on floppy disk, modem xfr, or eprom (verification file will be returned via same media) 2. an attached specification if not using ti standard specification as incorporated in ti's applicable device data book. company name: street address: street address: city: state zip contact mr./ms.: phone: ( ) ext.: customer purchase order number: customer part number: customer application: customer print number *yes: # no: (std. spec to be followed) *if yes: customer must provide oprinto to ti w/ncrf for approval before rom code processing starts. TMS370 device: ti customer rom number: (provided by texas instruments) contact options for the 'a' version TMS370 microcontrollers oscillator frequency min typ max [] external drive (clkin) [] crystal [] ceramic resonator low power modes [] enabled [] disabled watchdog counter [] standard [] hard enabled [] simple counter clock type [] standard (/4) [] pll (/1) [] supply voltage min: max: (std range: 4.5v to 5.5v) note: non 'a' version rom devices of the TMS370 microcontrollers will have the alow-power modes enabledo, adivide-by-4o clock, and astandardo watchdog options. see the TMS370 family user's guide (literature number spnu127) or the TMS370 family data manual (literature number spns014b). temperature range [] 'l': 0 to 70 c (standard) [] 'a': 40 to 85 c [] 't': 40 to 105 c package type [] 'n' 28-pin pdip [] afno 44-pin plcc [] afno 28-pin plcc [] afno 68-pin plcc [] ano 40-pin pdip [] anmo 64-pin psdip [] anjo 40-pin psdip (formerly known as n2) symbolization bus expansion [] ti standard symbolization [] ti standard w/customer part number [] customer symbolization (per attached spec, subject to approval) [] yes [] no non-standard specifications: all non-standards specifications must be approved by the ti engineering staff: if the customer requires expedited production ma terial (i.e., product which must be started in process prior to prototype approval and full production release) and non-standard spec issues are not resolved to the satisfaction of both the customer and ti in time for a scheduled shipment, the specification parameters in question will be pro cessed/tested to the standard ti spec. any such devices which are shipped without conformance to a mutually approved spec, will be identified by a 'p' in the symbolization preceding the ti part number. release authorization: this document, including any referenced attachments, is and will be the controlling document for all orders placed for this ti custom device. any changes must be in writing and mutually agreed to by both the customer and ti. the prototype cycletime commences when this document is signe d off and the verification code is approved by the customer. 1. customer: date: 2. ti: field sales: marketing: prod. eng.: proto. release: figure 8. sample new code release form
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 31 post office box 1443 ? houston, texas 772511443 table 17 is a collection of all the peripheral file frames used in the 'cx32 (provided for a quick reference). table 17. peripheral file frame compilation system configuration registers pf bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reg p010 cold start osc power pf auto wait osc flt flag mc pin wpo mc pin data e m p/ m c mode sccr0 p011 e e e auto wait disable e memory disable e e sccr1 p012 halt / standby pwrdwn / idle e bus stest cpu stest e int1 nmi privilege disable sccr2 p013 to p016 reserved p017 int1 flag int1 pin data e e e int1 polarity int1 priority int1 enable int1 p018 int2 flag int2 pin data e int2 data dir int2 data out int2 polarity int2 priority int2 enable int2 p019 int3 flag int3 pin data e int3 data dir int3 data out int3 polarity int3 priority int3 enable int3 p01a busy e e e e ap w1w0 exe deectl p01b reserved p01c busy vpps e e e e w0 exe epctll p01d p01e p01f reserved digital port control registers p020 reserved aport1 p021 port a control register 2 (must be 0) aport2 p022 port a data adata p023 port a direction adir p024 to p02b reserved p02c port d control register 1 (must be 0) e port d control register 1 (must be 0) e e e dport1 p02d port d control register 2 (must be 0) 2 e port d control register 2 (must be 0) 2 e e e dport2 p02e port d data e port d data e e e ddata p02f port d direction e port d direction e e e ddir pact module register memory map p040 deftim ovrfl int ena deftim ovrfl int flag cmd/def area ena fast mode select pact prescale select3 pact prescale select2 pact prescale select1 pact prescale select0 pactscr p041 cmd/def area int ena e cmd/def area start bit 5 cmd/def area start bit 4 cmd/def area start bit 3 cmd/def area start bit 2 e e cdstart 2 to configure d3 as sysclk, set port d register 2 = 08h.
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 32 post office box 1443 ? houston, texas 772511443 table 17. peripheral file frame compilation (continued) pf bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reg pact module register memory map (continued) p042 e cmd/def area end bit 6 cmd/def area end bit 5 cmd/def area end bit 4 cmd/def area end bit 3 cmd/def area end bit 2 e e cdend p043 1 1 buffer pointer bit 5 buffer pointer bit 4 buffer pointer bit 3 buffer pointer bit 2 buffer pointer bit 1 e bufptr p044 reserved p045 pact rxrdy pact txrdy pact parity pact fe pact sci rx int ena pact sci tx int ena e pact sci sw reset scictlp p046 pact rxdt7 pact rxdt6 pact rxdt5 pact rxdt4 pact rxdt3 pact rxdt2 pact rxdt1 pact rxdt0 rxbufp p047 pact txdt7 pact txdt6 pact txdt5 pact txdt4 pact txdt3 pact txdt2 pact txdt1 pact txdt0 txbufp p048 pact op8 state pact op7 state pact op6 state pact op5 state pact op4 state pact op3 state pact op2 state pact op1 state pstate p049 cmd/def int 7 flag cmd/def int 6 flag cmd/def int 5 flag cmd/def int 4 flag cmd/def int 3 flag cmd/def int 2 flag cmd/def int 1 flag cmd/def int 0 flag cdflags p04a cp2 int ena cp2 int flag cp2 capt rising edge cp2 capt falling edge cp1 int ena cp1 int flag cp1 capt rising edge cp1 capt falling edge cpctl1 p04b cp4 int ena cp4 int flag cp4 capt rising edge cp4 capt falling edge cp3 int ena cp3 int flag cp3 capt rising edge cp3 capt falling edge cpctl2 p04c cp6 int ena cp6 int flag cp6 capt rising edge cp6 capt falling edge cp5 int ena cp5 int flag cp5 capt rising edge cp5 capt falling edge cpctl3 p04d buffer half/full int ena buffer half/full int flag input capt prescale select 3 input capt prescale select 2 input capt prescale select 1 cp6 event only event counter sw reset op/ set/clr select cppre p04e watchdog reset key wdrst p04f pact stest pact suspend pact group 1 priority pact group 2 priority pact group 3 priority pact mode select pact wd prescale select 1 pact wd prescale select 0 pactpri p070 convert start sample start ref volt select2 ref volt select1 ref volt select0 ad input select2 ad input select1 ad input se- lect0 adctl p071 e e e e e ad ready ad int flag ad int ena adstat p072 a/d conversion data register addata p073 to p07c reserved p07d port e data input register adin p07e port e input enable register adena p07f ad stest ad priority ad espen e e e e e adpri
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 33 post office box 1443 ? houston, texas 772511443 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 2 supply voltage range,v cc1 (see note 3) 0.6 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, all pins except mc 0.6 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . mc 0.6 v to 14 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input clamp current, i ik (v i < 0 or v i > v cc1 ) 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output clamp current, i ok (v o < 0 or v o > v cc1 ) 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous output current per buffer, i o (v o = 0 to v cc1 ) (see note 4) 10 ma . . . . . . . . . . . . . . . . . . . . . . . . maximum i cc current 170 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . maximum i ss current 170 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous power dissipation 800 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating free-air temperature, t a : l version 0 c to 70 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a version 40 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t version 40 c to 105 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 3. unless otherwise noted, all voltage values are with respect to v ss1 . 4. electrical characteristics are specified with all output buffers loaded with specified i o current. exceeding the specified i o current in any buffer can affect the levels on other buffers. recommended operating conditions min nom max unit v cc1 supply voltage (see note 3) 4.5 5 5.5 v v cc1 ram data retention supply voltage (see note 5) 3 5.5 v v cc3 analog supply voltage (see note 3) 4.5 5 5.5 v v ss3 analog supply ground 0.3 0 0.3 v v il low level in p ut voltage all pins except mc v ss1 0.8 v v il lo w- le v el inp u t v oltage mc, normal operation v ss1 0.3 v v hi h l l i t lt all pins except mc, xtal2 / clkin, and reset 2 v cc1 v v ih high-level input voltage xtal2 / clkin 0.8 v cc1 v cc1 v reset 0.7 v cc1 v cc1 eeprom write protect override (wpo) 11.7 12 13 v mc mc (mode control) voltage eprom programming voltage (v pp ) 13 13.2 13.5 v microcomputer v ss1 0.3 l version 0 70 t a operating free-air temperature a version 40 85 c t version 40 105 notes: 3. unless otherwise noted, all voltage values are with respect to v ss1 . 5. reset must be externally activated when v cc1 or sysclk is not within the recommended operating range.
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 34 post office box 1443 ? houston, texas 772511443 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit v ol low-level output voltage i ol = 1.4 ma 0.4 v v oh high level out p ut voltage i oh = 50 m a 0.9 v cc1 v v oh high - le v el o u tp u t v oltage i oh = 2 ma 2.4 v 0 v v i 0.3 v 10 m a i i in p ut current mc 0.3 v < v i 13 v 650 m a i i inp u t c u rrent 12 v v i 13 v 2 50 ma i / o pins 0 v v i v cc1 10 m a i ol low-level output current v ol = 0.4 v 1.4 ma i oh high level out p ut current v oh = 0.9 v cc1 50 m a i oh high - le v el o u tp u t c u rrent v oh = 2.4 v 2 ma see notes 6 and 7 35 45 sysclk = 5 mhz supply current (operating mode) see notes 6 and 7 25 35 ma y(g) osc power bit = 0 sysclk = 3 mhz ma see notes 6 and 7 10 14 sysclk = 0.5 mhz see notes 6 and 7 12 17 sysclk = 5 mhz i cc1 supply current (standby mode) see notes 6 and 7 8 13 ma i cc1 y( ) osc power bit = 0 sysclk = 3 mhz ma see notes 6 and 7 3 4 sysclk = 0.5 mhz suppl y current (standby mode) see notes 6 and 7 sysclk = 3 mhz 6 8.6 ma y( ) osc power bit = 1 see notes 6 and 7 sysclk = 0.5 mhz 2 3.0 ma su pp ly current (halt mode) see note 6 15 40 m a s u ppl y c u rrent (halt mode) xtal2/clkin < 0.2 v m a 2 input current i pp will be a maximum of 50 ma only when programming eprom. notes: 6. single chip mode, ports configured as inputs or outputs with no load. all inputs 0.2 v or v cc 0.2v. 7. xtal2/clkin is driven with an external square-wave signal with 50% duty cycle and rise and fall times less than 10 ns. curren t can be higher with a crystal oscillator. at 5-mhz sysclk, this extra current = 0.01 ma x (total load capacitance + crystal capa citance in pf).
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 35 post office box 1443 ? houston, texas 772511443 external clock signal xtal1 xtal2/clkin c2 (see note a) c1 (see note a) crystal/ceramic resonator (see note b) xtal1 xtal2/clkin c3 (see note a) notes: a. the values of c1 and c2 are typically 15 pf and c3 value is typically 50 pf. see the manufacturer's recommendations for ceramic resonators. b. the crystal/ceramic resonator frequency is four times the reciprocal of the system clock period. figure 9. recommended crystal/clock connections 1.2 k w 20 pf v o load voltage case 1: v o = v oh = 2.4 v; load voltage = 0 v case 2: v o = v ol = 0.4 v; load voltage = 2.1 v note a: all measurements are made with the pin loading as shown unless otherwise noted. all measurements are made with xtal2/clk in driven by an external square wave signal with a 50% duty cycle and rise and fall times less than 10 ns unless otherwise stated. figure 10. typical output load circuit (see note a) v cc gnd 300 w 20 w i/o pin data output enable v cc gnd int1 6 k w 20 w 30 w figure 11. typical buffer circuitry
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 36 post office box 1443 ? houston, texas 772511443 parameter measurement information timing parameter symbology timing parameter symbols have been created in accordance with jedec standard 100. in order to shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: ar array pgm program b byte sc sysclk ci xtal2/clkin lowercase subscripts and their meanings are: c cycle time (period) su setup time d delay time v valid time f fall time w pulse duration (width) r rise time the following additional letters are used with these meanings: h high l low v valid all timings are measured between high and low measurement points as indicated in figure 12 and figure 13. 0.8 v (low) 2 v (high) 0.8 v (low) 0.8 v cc v (high) figure 12. xtal2/clkin measurement points figure 13. general measurement points
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 37 post office box 1443 ? houston, texas 772511443 external clocking requirements for clock divided by 4 (see note 8 and figure 14) no. parameter min max unit 1 t w(cl) pulse duration, xtal2/clkin (see note 9) 20 ns 2 t r(cl) rise time, xtal2/clkin 30 ns 3 t f(ci) fall time, xtal2/clkin 30 ns 4 t d(cih-scl) delay time, xtal2/clkin rise to sysclk fall 100 ns clkin crystal operating frequency 2 20 mhz sysclk internal system clock operating frequency 2 0.5 5 mhz 2 sysclk = clkin/4 notes: 8. for v il and v ih , refer to recommended operating conditions. 9. this pulse may be either a high pulse, as illustrated below, which extends from the earliest valid high to the final valid hi gh in an xtal2/clkin cycle or a low pulse, which extends from the earliest valid low to the final valid low in an xtal2/clkin cycle. xtal2/clkin 3 2 1 4 sysclk figure 14. external clock timing for divide-by-4 external clocking requirements for clock divided by 1 (pll) (see note 8 and figure 15) no. parameter min max unit 1 t w(cl) pulse duration, xtal2/clkin (see note 9) 20 ns 2 t r(cl) rise time, xtal2/clkin 30 ns 3 t f(ci) fall time, xtal2/clkin 30 ns 4 t d(cih-sch) delay time, xtal2/clkin rise to sysclk rise 100 ns clkin crystal operating frequency 2 5 mhz sysclk internal system clock operating frequency 3 2 5 mhz 3 sysclk = clkin/1 notes: 8. for v il and v ih , refer to recommended operating conditions. 9. this pulse can be either a high pulse, as illustrated below, which extends from the earliest valid high to the final valid hi gh in an xtal2/clkin cycle or a low pulse, which extends from the earliest valid low to the final valid low in an xtal2/clkin cycle. 4 3 2 1 xtal2/clkin sysclk figure 15. external clock timing for divide-by-1
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 38 post office box 1443 ? houston, texas 772511443 switching characteristics and timing requirements (see note 10 and figure 16) no. parameter min max unit 5 t cycle time sysclk (system clock) divide-by-4 200 2000 ns 5 t c c y cle time , sysclk (s y stem clock) divide-by-1 200 500 ns 6 t w(scl) pulse duration, sysclk low 0.5 t c 20 0.5 t c ns 7 t w(sch) pulse duration, sysclk high 0.5 t c 0.5 t c + 20 ns note 10: t c = system clock cycle time = 1 / sysclk sysclk 5 6 7 figure 16. sysclk timing general purpose output signal switching time requirements (see figure 17) min nom max unit t r rise time 30 ns t f fall time 30 ns t f t r figure 17. signal switching timing recommended eeprom timing requirements for programming min max unit t w(pgm)b pulse duration, programming signal to ensure valid data is stored (byte mode) 10 ms t w(pgm)ar pulse duration, programming signal to ensure valid data is stored (array mode) 20 ms recommended eprom operating conditions for programming min nom max unit v cc supply voltage 4.75 5.5 6 v v pp supply voltage at mc pin 13 13.2 13.5 v i pp supply current at mc pin during programming (v pp = 13 v) 30 50 ma sysclk system clock divide-by-4 0.5 5 mhz sysclk s y stem clock divide-by-1 2 5 mh z recommended eprom timing requirements for programming min nom max unit t w(epgm) pulse duration, programming signal (see note 11) 0.40 0.50 3 ms note 11: programming pulse is active when both exe (epctl.0) and v pps (epctl.6) are set.
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 39 post office box 1443 ? houston, texas 772511443 adc1 converter the adc1 converter has a separate power bus for its analog circuitry. these pins are referred to as v cc3 and v ss3 . the purpose is to enhance adc1 performance by preventing digital switching noise of the logic circuitry that can be present on v ss1 and v cc1 from coupling into the adc1 analog stage. all adc1 specifications are given with respect to v ss3 unless otherwise noted. resolution 8-bits (256 values) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . monotonic yes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output conversion mode 00h to ffh (00 for v i v ss3 ; ff for v i v ref ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . conversion time (excluding sample time) 164 t c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . recommended operating conditions min nom max unit v cc3 analog su pp ly voltage 4.5 5 5.5 v v cc3 analog s u ppl y v oltage v cc1 0.3 v cc1 +0.3 v v ss3 analog ground v ss1 0.3 v ss1 +0.3 v v ref non-v cc3 reference 2 2.5 v cc3 v cc3 + 0.1 v analog input for conversion v ss3 v ref v 2 v ref must be stable, within 1/2 lsb of the required resolution, during the entire conversion time. operating characteristics over recommended ranges operating conditions parameter min max unit absolute accuracy 3 v cc3 = 5.5 v v ref = 5.1 v 1.5 lsb differential/integral linearity error 3 v cc3 = 5.5 v v ref = 5.1 v 0.9 lsb i cc3 analog su pp ly current converting 2 ma i cc3 analog s u ppl y c u rrent nonconverting 5 m a i i input current, an0 an7 0 v v i 5.5 v 2 m a i ref input charge current 1 ma z f source im p edance of v f sysclk 3 mhz 24 k w z ref so u rce impedance of v ref 3 mhz < sysclk 5 mhz 10 k w 3 absolute resolution = 20 mv. at v ref = 5 v, this is one lsb. as v ref decreases, lsb size decreases; therefore, the absolute accuracy and differential/integral linearity errors in terms of lsbs increase. excluding quantization error of 1/2 lsb
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 40 post office box 1443 ? houston, texas 772511443 adc1 converter (continued) the adc1 module allows complete freedom in design of the sources for the analog inputs. the period of the sample time is user-defined so that the high-impedance can be accommodated without penalty to the low-impedance sources. the sample period begins when the sample start bit of the adc1 control register (adctl.6) is set to 1. the end of the signal sample period occurs when the conversion bit (convert start, adctl.7) is set to 1. after a hold time, the converter will reset the sample start and convert start bits, signaling that a conversion has started and that the analog signal can be removed. analog timing requirements (see figure 18) min max unit t su(s) setup time, analog to sample command 0 ns t h(an) hold time, analog input from start of conversion 18t c ns t w(s) pulse duration, sample time per kilo- w of source impedance 2 1 m s/k w 2 the value given is valid for a signal with a source impedance > 1 k w . if the source impedance is < 1 k w , use a minimum sampling time of 1 m s. analog in sample start convert start analog stable t h(an) t w(s) t su(s) figure 18. analog timing table 18 is designed to aid the user in referencing a device part number to a mechanical drawing. the table shows a cross-reference of the device part number to the TMS370 generic package name and the associated mechanical drawing by drawing number and name. table 18. TMS370cx32 family package type and mechanical cross-reference pkg type (mil pin spacing) TMS370 generic name pkg type no. and mechanical name device part numbers fn 44 pin (50-mil pin spacing) plastic leaded chip carrier (plcc) fn(s-pqcc-j**) plastic j-leaded chip carrier TMS370c032afna TMS370c032afnl TMS370c032afnt TMS370c332afna TMS370c332afnl TMS370c332afnt TMS370c732afnt fz 44 pin (50-mil pin spacing) ceramic leaded chip carrier (clcc) fz(s-cqcc-j**) j-leaded ceramic chip carrier se370c732afzt
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 41 post office box 1443 ? houston, texas 772511443 mechanical data fn (s-pqcc-j**) plastic j-leaded chip carrier 4040005 / b 03/95 20 pin shown 0.026 (0,66) 0.032 (0,81) d2 / e2 0.020 (0,51) min 0.180 (4,57) max 0.120 (3,05) 0.090 (2,29) d2 / e2 0.013 (0,33) 0.021 (0,53) seating plane max d2 / e2 0.219 (5,56) 0.169 (4,29) 0.319 (8,10) 0.469 (11,91) 0.569 (14,45) 0.369 (9,37) max 0.356 (9,04) 0.456 (11,58) 0.656 (16,66) 0.008 (0,20) nom 1.158 (29,41) 0.958 (24,33) 0.756 (19,20) 0.191 (4,85) 0.141 (3,58) min 0.441 (11,20) 0.541 (13,74) 0.291 (7,39) 0.341 (8,66) 18 19 14 13 d d1 1 3 9 e1 e 4 8 min max min pins ** 20 28 44 0.385 (9,78) 0.485 (12,32) 0.685 (17,40) 52 68 84 1.185 (30,10) 0.985 (25,02) 0.785 (19,94) d/e 0.395 (10,03) 0.495 (12,57) 1.195 (30,35) 0.995 (25,27) 0.695 (17,65) 0.795 (20,19) no. of d1 / e1 0.350 (8,89) 0.450 (11,43) 1.150 (29,21) 0.950 (24,13) 0.650 (16,51) 0.750 (19,05) 0.004 (0,10) m 0.007 (0,18) 0.050 (1,27) notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. falls within jedec ms-018
TMS370cx32 8-bit microcontroller spns015c february 1990 revised february 1997 42 post office box 1443 ? houston, texas 772511443 mechanical data fz (s-cqcc-j**) j-leaded ceramic chip carrier 4040219 / b 03/95 0.180 (4,57) 0.140 (3,55) c 0.020 (0,51) 0.032 (0,81) a b a b 0.025 (0,64) r typ 0.026 (0,66) 0.120 (3,05) 0.155 (3,94) 0.014 (0,36) 0.120 (3,05) 0.040 (1,02) min 0.090 (2,29) 0.040 (1,02) 45 a min max 0.485 (12,32) (12,57) 0.495 0.455 (11,56) (10,92) 0.430 max min bc min max 0.410 (10,41) (10,92) 0.430 0.630 0.610 0.630 0.655 0.695 0.685 (16,00) (15,49) (16,00) (16,64) (17,65) (17,40) 0.740 0.680 0.730 0.765 0.795 0.785 (18,79) (17,28) (18,54) (19,43) (20,19) (19,94) pins** 28 44 52 no. of jedec mo-087ac mo-087ab mo-087aa outline 28 lead shown seating plane (at seating plane) 1 426 25 19 18 12 11 5 0.050 (1,27) 0.930 0.910 0.930 0.955 0.995 0.985 (23,62) (23,11) (23,62) (24,26) (25,27) (25,02) 68 mo-087ad notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. this package can be hermetically sealed with a ceramic lid using glass frit.
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (acritical applicationso). ti semiconductor products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the customer's risk. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 1998, texas instruments incorporated

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